Various problems arise when a fast semiconductor integrated circuit (IC) interacts with the outside world. One problem is that the voltages on the internal supply lines often "bounce" up and down. The bounce can cause the IC to operate improperly when it responds to an input signal having a slowly changing voltage. The problem normally becomes more serious as the IC speed increases.
In explanation of supply line bounce, FIG. 1 illustrates a portion of a digital IC 10 that receives largely constant external supply voltages V.sub.HH and V.sub.LL at respective externally accessible supply terminals (or pads) T.sub.H and T.sub.L. V.sub.HH is greater than V.sub.LL. IC 10 produces a circuit output voltage V.sub.O at an externally accessible output terminal T.sub.O in response to a circuit input voltage V.sub.I received at an externally accessible input terminal T.sub.I. A capacitor C.sub.O, which may be real or parasitic, is connected between terminal T.sub.O and the V.sub.LL supply.
The illustrated portion of IC 10 is a conventional inverting driver powered by high and low internal supply voltages V.sub.H and V.sub.L provided on lines connected respectively to terminals T.sub.H and T.sub.L. Responsive to an internal input voltage V.sub.A supplied on a line connected to terminal T.sub.I, the driver produces an internal output voltage V.sub.D on a line connected to terminal T.sub.O. Parasitic inductances L.sub.L, L.sub.H, L.sub.I, and L.sub.O are respectively associated with the lines carrying voltages V.sub.L, V.sub.H, V.sub.A, and V.sub.D.
The driver consists of an input inverter 12, an intermediate inverter 14, and an output inverter 16, each of which is progressively larger so as to provide progressively more current. Inverter 12 is formed with complementary input field-effect transistors (FET's) Q1.sub.N and Q1.sub.P whose gates receive voltage V.sub.A and whose interconnected drains provide an inverter output voltage V.sub.B logically inverse to voltage V.sub.A. Inverter 14, which is typically configured the same as inverter 12, generates a voltage V.sub.C inverse to voltage V.sub.B. Inverter 16 consists of complementary output FET's Q2.sub.N and Q2.sub.P whose gates receive voltage V.sub.C and whose interconnected drains provide voltage V.sub.D as the inverse of voltage V.sub.C. FET's Q1.sub.N and Q2.sub.N are N-channel devices whose sources are connected to the V.sub.L supply line. FET's Q1.sub.P and Q2.sub.P are P-channel transistors having their sources tied to the V.sub.H supply line.
Returning to inverter 12, it changes state as the voltage difference V.sub.A -V.sub.L passes an inverter threshold voltage V.sub.T. Threshold V.sub.T is at a nominal value V.sub.S when internal supply voltages V.sub.L and V.sub.H are respectively at (or very close to) V.sub.LL and V.sub.HH. Accordingly, inverter 12 switches from a high logic state to a low logic state as voltage V.sub.A rises above V.sub.LL +V.sub.S. This is manifested in voltage V.sub.B which goes from a high voltage level close to V.sub.HH to a low voltage level close to V.sub.LL. When V.sub.A later drops below V.sub.LL +V.sub.S, inverter 12 switches from its low logic state to its high logic state. V.sub.B then rises from V.sub.LL back up to V.sub.HH.
Consider what happens if input V.sub.I changes very slowly. With reference to FIG. 2 which roughly shows how certain voltages vary with time for IC 10, assume that V.sub.I is initially low. Also assume that V.sub.L and V.sub.H are respectively at V.sub.LL and V.sub.HH. V.sub.A is then low, causing V.sub.B to be at V.sub.HH. V.sub.C is low so that FET Q2.sub.N is turned off and FET Q2p is turned on. V.sub.D and V.sub.O are both at V.sub.HH. Capacitor C.sub.O is charged to a high level.
As V.sub.I rises slowly, V.sub.A tracks V.sub.I closely. Inductance L.sub.I does not have any significant effect on V.sub.A. At a time t.sub.1, V.sub.A starts to go above V.sub.LL +V.sub.S. This causes V.sub.B to drop rapidly to V.sub.LL. V.sub.C goes high to turn FET Q2.sub.N on and FET Q2.sub.P off. V.sub.D drops rapidly to V.sub.LL. At a time t.sub.2 depending on the transmission delays through inverters 14 and 16, capacitor C.sub.O starts discharging to the V.sub.LL supply by way of a path through elements L.sub.O, Q2.sub.N, and L.sub.L to pull V.sub.O rapidly down to V.sub.LL.
The current flowing through this path varies with time in a non-linear manner. Since the voltage across an inductor is the inductance times the time rate of change of current flowing through the inductor, a positive voltage builds up across inductance L.sub.L, reaching a maximum at a time t.sub.3. A positive (or upward going) spike in V.sub.L thereby occurs at t.sub.3 as shown in FIG. 2. The V.sub.L spike at t.sub.3 is the "first" spike in a set of timewise contiguous pairs of alternating spikes that die out quickly, of which only the first pair of alternating spikes are actually shown in FIG. 2. The same applies to the further supply line spikes discussed below for FIG. 2 and to the supply line spikes illustrated in the other time diagrams herein.
The V.sub.L spike at t.sub.3 is often so high that V.sub.A -V.sub.L temporarily drops below threshold V.sub.T. This is true even though the attendant reduction of the difference between V.sub.H and V.sub.L during the positive V.sub.L spike reduces V.sub.T somewhat. See shaded area 18 in FIG. 2. (Note that the comparison of V.sub.L to V.sub.A -V.sub.T shown in the various time diagrams herein is equivalent to the comparison of V.sub.A -V.sub.L to V.sub.T which is more difficult to illustrate graphically.) Inverter 12 then makes a pair of rapid changes in logic state at approximately a time t.sub.4, causing V.sub.B to spike upwards. In turn, the V.sub.B spike causes a positive V.sub.O spike to occur at a time t.sub.5. Even if the C.sub.O discharge current flowing through FET Q2.sub.N in output inverter 16 were not sufficient in itself to cause the V.sub.O spike, it could be produced as the result of several such output inverters acting in unison in IC 10.
The rapid charging and discharging of capacitor C.sub.O that occur with the V.sub.O spike produce a negative (or downward going) V.sub.H spike followed by another positive V.sub.L spike. In the example shown in FIG. 2, neither of the further spikes is sufficient to cause V.sub.A -V.sub.L to fall below V.sub.T. However, if V.sub.I were rising slower than indicated, the further supply line bounce could cause inverter 12 to make additional undesired transitions, thereby resulting in further V.sub.O spiking.
The same situation arises if V.sub.I drops slowly, except that the polarities and supply lines are reversed. The first spike is a negative V.sub.H spike that results from the rapid charging of capacitor C.sub.O by way of a path through elements L.sub.H, Q2.sub.p, and L.sub.O.
The V.sub.O spikes and the corresponding spikes in V.sub.B, V.sub.C, and V.sub.D can be disastrous. They can cause a circuit (such as a flip-flop) responsive to V.sub.O, V.sub.B, V.sub.C, or V.sub.D to be set in a wrong state.
To overcome the bounce problem, one might consider replacing inverter 12 with a device (such as a Schmitt trigger) having a pair of separate static voltage thresholds. While static hysteresis might be useful in certain applications, it is not effective if the two thresholds must lie within a narrow voltage range. A solution that entails a single static threshold is desirable.